Area-efficient programmable arbiter for inter-layer communications in 3-D network-on-chip
نویسندگان
چکیده
منابع مشابه
Adaptive Inter-router Links for Low-Power, Area-Efficient and Reliable Network-on-Chip (NoC) Architectures
The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power consumption, area overhead and performance of the entire NoC is influenced by the router buffers, research efforts have targeted optimized router buffer design. In this paper, we propose iDEAL inter-router, dual-function energy ...
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Network-on-chip (NoC) is an effective on-chip communication technique; the core function of the crossbar schedulers used in the routers located into an NoC is arbitration which is required as and when a number of input ports of a router requests for a particular output port. The design of the arbiters is of paramount importance as the parameters like delay and area of the arbiters play a vital ...
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ژورنال
عنوان ژورنال: Open Computer Science
سال: 2012
ISSN: 2299-1093
DOI: 10.2478/s13537-012-0006-8